Generally, in the fabrication of IC devices, lithography processes may be utilized to print/pattern cavities, trenches, recessed-areas, and other elements for creating various components and circuits. Various process operations, such as etching, may then be performed on the underlying layer of material or substrate through patterned block or cut masks. However, with advancements in processes utilized to manufacture IC devices as well as industry demand for more efficient and smaller sized devices, physical dimensions of the elements as well as their proximity to each other are reduced. As a result, spaces between adjacent elements may be reduced causing a reduction in error tolerance/thresholds in various fabrication processes. For example, in scaling of fin-type devices (e.g., 7 nm or smaller), a smaller fin-pitch (FP) and reduced space between the silicon (Si) fins render forming and removing of the fins challenging.
FIG. 1 schematically illustrates an example layout diagram of a FINFET device including cells 101, 103, and 105 that include a various number of fins 107. For example, each cell includes a p-FET and n-FET device, wherein the cells 101, 103, and 105 include four active fins, three active fins, and two active fins, respectively, for each device. However, since four active fins are formed initially per device in each cell, cut-masks 109 and 111 are utilized to remove a subset of fins 113 that are not necessary in the cells 103 and 105. Here, a total tolerance level for placement/alignment of a cut-mask (e.g. 109) would be equal to a space 115 between adjacent fins (e.g. 18 nm or +/−9 nm for a 6 nm fin width). As noted, with reduced spaces between the adjacent fins or elements in highly integrated devices, accurate alignment of edges 117 (e.g. of the masks 109/111) can become increasingly challenging and prone to errors, which can impact the fabrication efficiencies and reliability of the IC devices.
Therefore, a need exists for a methodology enabling fin generation in tapered FINFET devices with increased edge placement error (EPE) tolerance with no additional masks.